1. Field of the Invention
The present invention relates to a circuit for testing integrated circuit devices. More particularly, the present invention relates to a circuit for testing integrated circuit devices employing a scan path.
2. Description of the Prior Art
The degree of integration of integrated circuits has been improved rapidly by virtue of the progress in minute processing technique, and is expected to be further improved in future. As the degree of integration is improved, that is, the number of gates are increased, the difficulty in testing integrated circuit devices has been exponentially enhanced. Now, how easily a device can be tested is determined by two factors, namely, how easily defects in the circuits connected to terminals are detected, i.e. observability, and how easily the terminals are set at desirable logic values, i.e. controllability. In general, in a large scale logic circuit network, both monitoring and controlling of a terminal which is not easily accessed on the circuit become difficult.
A scan test method is known as an example of a method for testing integrated circuit devices. In the scan test method, register circuits having the function of shift registers are inserted at appropriate portions in the logic circuit network. These register circuits are connected by one shift register path. In testing, a test pattern is serially inputted from outside the chip to set prescribed data in respective registers. A desired logic signal is applied to a logic circuit connected to a data output terminal of each of these registers to effect logic operation. The result is taken in to the register from a parallel input terminal of the register, and the data is serially outputted outside the chip. By monitoring the outputted data, the ease in monitoring and controlling of a terminal which is not easily accessed can be enhanced in a large scale logic circuit network.
FIG. 1 is a block diagram showing an example of a conventional scan path type test circuit. In FIG. 1, the test circuit is for testing circuit blocks 29, 30 and 31. Scan registers 8, 9 and 10 and data selectors 20, 21 and 22 are connected between the circuit blocks 29 and 30. The data selectors 20, 21 and 22 select either the output of the circuit block 29 or the outputs from the scan registers 8, 9 and 10 to output the same to the circuit block 30 of the succeeding stage.
In the similar manner, scan registers 11, 12 and 13 and data selectors 23, 24 and 25 are connected between the circuit blocks 30 and 31. The data selectors 23, 24 and 25 respectively select either the output of the circuit block 30 or the outputs of the scan registers 11, 12 and 13 to output the same to the circuit block 31 in the succeeding stage. In addition, scan registers 14, 15 and 16 and data selectors 26, 27 and 28 are connected to the output of the circuit block 31. These data selectors 26, 27 and 28 select either the output of the circuit block 31 or the outputs of the scan registers 14, 15 and 16 to output the same.
Output ends of respective circuit blocks 29 to 31 are connected to the data input terminals D of the scan registers 8 to 16 and to the data input terminals D of the data selectors 20 to 28. The test data input terminals TD of the data selectors 20 to 28 are connected to output terminals Q of the corresponding scan registers. The test mode selecting terminal 44 is connected to respective mode selecting terminals MS of the data selectors 20 to 28. A scan in terminal 2 is connected to a scan in terminal SI of the scan register 8, and an output terminal Q of the scan register 8 is connected to the scan in terminal SI of the scan register 9. Similarly, output terminals of the scan registers 9 to 16 are respectively connected to the scan in terminals SI of the scan registers in the succeeding stage. As a result, a shift register path is formed between the scan in terminal 2 and a scan out terminal 32.
A normal data is inputted to the circuit block 29 in the first stage through data input terminals 3 to 5. In correspondence with scan clock input terminals T1 and data clock input terminals TD of the scan registers 8 to 16, clock input terminals 1 and 7 are provided, and the clock signals applied thereto also serve as signals for selecting input data latched by the scan register 8 in the first stage. A clock signal for transferring data inputted and held in the scan register 8 of the first stage to the latch of the second stage provided in the scan register 8 is inputted to the clock input terminal 6.
FIG. 2 is a circuit diagram showing one example of the scan register shown in FIG. 1. In FIG. 2, inverters 35 and 36, and 38 and 39 respectively constitute latch circuits. The latch circuit in the preceding stage and the latch circuit in the succeeding stage are connected with each other by a transmission gate 37 formed of an n type MOS transistor. The transmission gate 37 becomes conductive in response to a clock signal inputted to a second scan clock input terminal T2, whereby the output of the latch circuit in the preceding stage is latched in the latch circuit in the succeeding stage. Transmission gates 33 and 34 constituted by n type MOS transistors are connected to the latch circuit in the preceding stage. A scan clock signal inputted to the first scan clock input terminal T1 is applied to the gate of the transmission gate 33. The transmission gate 33 latches the scan data inputted to the scan in terminal SI in the latch circuit 35 of the preceding stage in response to the scan clock signal. The transmission gate 34 latches the data inputted to the data input terminal D in the latch circuit of the preceding stage in response to a clock signal inputted to the data clock input terminal TD connected to the gate thereof.
FIG. 3 is a circuit diagram showing one example of the data selector shown in FIG. 1. In FIG. 3, a mode switching signal is applied to the mode selecting terminal MS. The mode switching signal is applied to one input end of the AND gate 42 and is inverted by an inverter 40 to be applied to one input end of the AND gate 41. A test data is inputted to the other input end of the AND gate 41 from the test data input terminal TD, and data is inputted to the other input end of the AND gate 42 from the data input terminal D. Respective outputs of the AND gates 41 and 42 arc outputted at an output terminal Y through an OR gate 43.
FIG. 4 is a timing diagram for illustrating the operation of the circuit shown in FIG. 1, FIG. 5 is a timing diagram for illustrating the operation of the scan register shown in FIG. 2, and FIG. 6 is a timing diagram for illustrating the operation of the data selector shown in FIG. 3.
The operation of the conventional circuit for testing semiconductor devices will be described in the following with reference to FIGS. 1 to 6.
First, description will be given of an normal operation. In this case, a "H" level signal is inputted as a test mode switching signal to the test mode selecting terminals 44, and the scan clock terminal 1 and the data clock terminal 7 are both set at "L" level. Consequently, input and output terminals of the corresponding circuit blocks 29, 30 and 31 are directly connected through respective data selectors 20 to 28.
More specifically, when a "H" level signal is applied to the mode selecting terminal MS of the data selector shown in FIG. 3, the AND gate 42 is opened and the data inputted to the data input terminal D is outputted to the output terminal Y through the AND gate 42 and the OR gate 43. Since respective outputs of the circuit blocks 29, 30 and 31 are directly connected to the data input terminals D of the data selectors 20 to 28, the input and output terminals between corresponding circuit blocks are directly connected with each other.
Meanwhile, in the test operation, the scan mode and test mode are successively repeated in the following manner to carry out testing of each circuit block.
(1) Scan Mode
In the scan mode, a "H" level signal is inputted to the test mode selecting terminal 44 as shown in FIG. 4(a) to set the scan mode. Consequently, each of the data selectors 20 to 28 outputs data inputted to the data input terminal D to the output terminal Y. Test data to be set in each of the scan registers 8 to 16 such as shown in FIG. 4(e) are inputted from the scan in terminal 2. These test data are successively scanned in to the scan registers 8 to 16 in synchronization with a first scan clock signal applied to the first scan clock terminal such as shown in FIG. 4(b) and with a second scan clock signal applied to the second scan clock terminal 6 such as shown in FIG. 4(c). The data clock input terminal 7 is set at a "L" level as shown in FIG. 4(d).
At the same time, output data of each of the circuit blocks 29 to 31 which were taken in at the last testing are successively scan-out from the scan out terminal 32. Description will be given in detail with reference to FIGS. 2 and 3.
First, in the scan register, the load drivability of the inverters 36 and 39 is smaller than that of the inverters 35 and 38. Therefore, when a clock signal shown in FIG. 5(a) is applied to the first scan clock terminal T1, the transmission gate 33 is opened and the data inputted to the scan in terminal SI such as shown in FIG. (d) is inputted and held in the latch circuit constituted by the inverters 35 and 36 (FIG. 5(e)). At the same time, the data held in the latch circuit constituted by the inverters 38 and 39 are outputted from the output terminal Q (FIG. 5(f)) and inputted to a succeeding scan register through a scan path.
On this occasion, a "H" level signal is also applied to the mode selecting terminal MS of the data selector, so that the data from the data input terminal D is outputted to the output terminal Y.
(2) Test Mode
When desired data are set in each of the scan registers 8 to 16, a "L" level signal is applied to the test mode selecting terminal 44 to select the test mode. Consequently, output data from the scan registers 8 to 16 are applied to each of the circuit blocks 30 and 31 through the test data input terminals TD of the data selectors 20 to 28. At the same time, additional desired test data are applied to the data input terminals 3 to 5. Thereafter, when the operation of the circuit blocks 29 to 31 are completed, one clock signal is applied to the data clock input terminal 7. Consequently, output signals of each of the circuit blocks 29 to 31 are held in the latch circuit in the respective scan registers 8 to 16 through the data input terminals D of the corresponding scan registers 8 to 16.
The operation will be described in the following with reference to FIGS. 2, 3, 5 and 6. First, in the scan register, when a clock signal shown in FIG. 6(b) is applied to the first scan clock terminal TD, the transmission gate 34 is opened and the data shown in FIG. 6(c) applied to the data input terminal D is inputted and held in the latch circuit of the first stage. On this occasion, since a "L" level mode selecting signal such as shown in FIG. 6(a) is applied to the mode selecting terminal MS of the data selector, the data from the test data input terminal TD such as shown in FIG. 6(d) is outputted to the output terminal Y. When one clock signal shown in FIG. 5(b) is applied to the next second scan clock terminal T2, the data in the latch circuit in the first stage of the scan register is shifted to the latch circuit of the second stage.
As described above, in a conventional circuit for testing semiconductor devices, the scan-in operation for setting test data in each of the scan registers 8 to 16 in the scan mode and the scan out operation for transmitting output data of each of the circuit blocks 29 and 30 taken in to the last testing should be in synchronization with clock signals, respectively, and the data should be successively transmitted through all scan registers 8 to 16 as shown in FIG. 4 (e) to n. Therefore, extra clock signals are required for the scan register group other than the scan registers provided before and after the test circuit block directly requiring the data, making it difficult to carry out the scan test in a short period of time.